Static Ultra Low-Voltage and High Performance CMOS NAND and NOR Gates

The need for novel digital logic styles for both ultra low supply voltage and low power applications is more and more evident. Especially, for hand held and mobile equipement, the power and supply voltage are important aspects to consider when designing both analog and digital systems. The digital circuits shrink rapidly with the introduction of recent semiconductor processes. The energy requirement for switching digital signals are at its minimum when the supply voltage is at its minimum[1]. However, the performance og digital systems is often characterized by Energy-Delay-Produc (EDP) which for most applications will entail a optimum for supply voltages close to the threshold voltage of the transistors used. Low supply voltage can be a requirement as a result from a power reduction strategy in digital circuitry. Floating-Gate (FG) gates have been proposed for Ultra-Low-Voltage (ULV) and Low-Power (LP) logic [2]. However, in modern CMOS technologies there are significant gate leakage which undermine nonvolatile FG circuits. FG gates implemented in a modern CMOS process require frequent initialization to avoid significant leakage. By using floating capacitances to the transistor gate terminals the semifloating-gate (SFG) nodes can have a different DC level than provided by the supply voltage headroom [2]. There are several approaches to FG CMOS logic [3, 4, 5]. The gates proposed in this paper are influenced by ULV non-volatile FG circuits [6]. The logic style characterized in this paper is based on dynamic and static ULV inverters presented in [7, 8]. In section 2 the static ULV differential domino inverter is described followed by a differential static ULV NAND and NOR gates in section 3.